LVDS (Low Voltage Differential Signal) drivers are used, in particular, in SCI (Scalable Coherent Interface) interfaces for transmitting data via point-to-point connections quickly. With SCI interfaces, much higher transmission speeds are achieved than with conventional data buses.
The principles for the shaping and dimensional design of LVDS drivers are specified in IEEE standard 1596.3-1996. An LVDS driver implemented in line with the standard produces a differential signal having a small amplitude of between 250 mV and 400 mV around a common mode voltage of Vcm=1.2 V, for example.
FIG. 1a) shows an example of the output signals which are output at the outputs Pout and Nout of an LVDS driver. As can be seen, the output signals have an amplitude of 400 mV and oscillate symmetrically around a common mode voltage VCM=1.2 V.
FIG. 2 shows a typical example of an LVDS driver for a CMOS technology with a supply voltage VDD of approximately 2.5 V. FIGS. 2a, b show a PMOS transistor (FIG. 2a) and an NMOS transistor (FIG. 2b) in the LVDS driver in an enlarged view, with the fundamental currents and voltages present on the components being shown. In this case, the index S stands for “Source”, D stands for “Drain” and G stands for “Gate”.
The outputs of the LVDS driver shown in FIG. 2 are denoted by Pout and Nout. The outputs produce the output signal shown in FIG. 1a. To connect the output voltage, a pull-up transistor P1 or P2 and a pull-down transistor N1 or N2 are provided at each output Pout and Nout. The transistors P1 and N1, and P2 and N2, are always in the opposite switching position and turn on and off in opposite senses.
If, by way of example, the transistor N1 has been switched to a low impedance, then the transistor P1 is high impedance, and the output Pout is at approximately 1.0 V. In the opposite switching position of the transistors P1, N1, the node Pout is at approximately 1.4 V.
The gate connections of the transistors P1, P2 and N1, N2 are respectively actuated by an input driver 1, 1′. The output signals A, B from the input drivers are likewise in opposite senses.
The LVDS driver 2 shown also comprises a tuning circuit 3 for adjusting the common mode voltage VCM.
With low supply voltages VDD of less than 2 V, as arise, by way of example, in IC circuits having a structured density of 0.18 μm and below, an LVDS driver in this configuration may result in problems when producing the differential signal, which are explained below with reference to FIG. 3.
FIGS. 3a) and 3b) respectively show a control signal (left-hand side) which is present at node A or B of the driver in FIG. 2 and also the associated switching edge at the respective signal output Pout or Nout (right-hand side). In this case, FIG. 3a) shows the switching response of the NMOS transistor N1 and FIG. 3b) shows the switching response of the PMOS transistor P2.
In the worst case, the supply voltage VDD is only 1.6 V (it is assumed that the supply voltage can vary between 1.6 V and 2.0 V. The control signal applied to the gate connection of the transistor Ni has an amplitude of 1.6 V. It is subsequently also assumed that the threshold voltage of the two transistors, i.e. the NMOS transistor N1 and the PMOS transistor P2, is VTH=400 mV. The source voltage of the transistor N1 is at 0.9 V. The voltage after which the NMOS transistor N1 changes to the low impedance state is thus 0.9 V+0.4 V=1.3 V (VGS−VTH>0).
As can be seen in FIG. 3a), the largest portion (81%) of the signal A has already been consumed before the NMOS transistor turns on. Only the remaining 300 mV actually drive the element.
By contrast, the PMOS transistor P2 requires only 31% of the control signal B in order to turn on the element. The source voltage of the transistor P2 is 1.5 V. That is to say that the transistor P2 switches to the low impedance state (VSG+VTH>0) at a gate voltage of only VG=1.1 V.
Another difference in the switching response of the NMOS and PMOS transistors N1 and P2 comes from the different operating ranges of the NMOS and PMOS elements. While the PMOS transistor P2 operates essentially in the linear range (VDS<VGS−VTH), the NMOS transistor changes from the saturation range (VDS<VGS−VTH) to the linear range (VDS>VGS−VTH) during the switching process. Since the effective turn-on voltage for the NMOS element (VGS−VTH) is small, the NMOS element is saturated at only VDS=300 mV. The source potential is approximately VS=0.9 V, which means that the element is already saturated when the drain potential is VD>1.2 V.
These different switching properties of PMOS and NMOS transistors result in switching edges which have different gradients, as shown in FIG. 1b), for example, and thus in distortion of the differential signal.
EP-0 536 536 A1 and U.S. Pat. No. 6,137,311 disclose LVDS drivers for producing a differential output signal at the driver outputs, whose pull-up and pull-down transistors are all in the form of PMOS transistors. However, the LVDS driver shown is not actuated in optimum fashion in relation to power loss and switching response from the PMOS transistors.